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101 about Memory Chip Testing

Tuesday, March 19, 2002 Introduction

PC Memories are getting bigger and cheaper

While price of PC memory has been going down, the megabyte has been going up. As recent as 1995, mainstream PC memory was selling at U$1 per megabyte. Due to the shrink in semiconductor device geometry and the PC economy, a megabyte of memory has gone down to as low as U$0.1 in 2001.

Although the new generation of Double Data Rate (DDR) memory has pulled this figure back up to U$0.27 / MB in the spring of 2002, it is at a point that we have to ask the question “Is it worth testing?” The answer is not exactly obvious. Perhaps we should examine how and why memories are tested at each level?

There is no 100% test

There is no 100% test on electronic memories. The trade off is between test time and confidence level. The more you test, the more confidence you can have provided that you follow a set of scientifically determined test patterns.

In modern memory, the smaller the semiconductor geometry goes, the more errors are induced by cosmic events. Cosmic rays, alpha particles, pollution, static discharge and environmental conditions can cause unpredictable failures, too.

How are memory actually tested ?

Memories are tested at different levels

Standard Test Patterns

Modern test pattern are build upon function fault model to uncover specific operational faults in a DRAM

AF= address decoder fault
SAF= stuck at fault
TF= transition fault
CF = coupling fault
CFid = Idempotent coupling fault
CFin = inversion coupling fault

DRAM Manufacturers

Semiconductor manufacturers’ concerned are mostly on the production process. They assume the DRAM circuitry designed is good. A lot of the AC parametric (timing) is only tested on small sample basis. Those parameters are listed on the specification sheet and are only guaranteed by design.

Since the semiconductor fault would most likely result in source and sink current difference, manufacturers would spend most effort in characterizing their transistors with dc parametric test. DC parametric test is a dc current/voltage test that would discover shorts and open plus dc abnormalities. Based on the statistics, manufacturers can predict their yield and tweak their process to improve yield. The DC parametric parameters are usually measured with an ATE memory tester (Automatic Test Equipment).

This is a relatively large machine made especially for detail test of memories. This machine usually comes with a measurement head for DC parametric tests. This measurement head has the capability to measure small DC current as low as 10 microampere.

Due to the imperfection of the process, there are a percentage of the DRAM dies that contains some faulty cells. Manufacturers improve their yield by applying a laser repair process. This process cuts away the known bad memory cells and replaces them with spare cells on the same die. In order to isolate the bad cells, manufacturers have to excite the entire memory array on the chip. That means every cell on the chip has to be exercised and tested. The test normally performed is called the “functional test”.

Selected test patterns are written into each cell and read back in special sequence and order to verify their proper functionality. In order to reduce the test time, parallel chip testing are performed usually with 8 to 16 chips in a row.

The above test is performed at the wafer level with automatic die stepping probes. A special ink jet is also used to color mark the bad dies. The wafer is then sent off for laser repair and to the backend for die separation and final packaging. Functional test is performed again at the post package level.

A chip manufacturer has great concern about contaminants in the processing that would hide problems for the initial period of time. Burn-in test is usually used to weed out this infant mortality problem. Life burn-in is by putting the chips into a chamber under elevated temperature, usually at 50-70 degree C for 72 hours. In order to save time, elevated supply voltage is used to accelerate the aging process. During the test, signals are applied to the DRAM to keep them in the active state.

Memory Module Manufacturers

Memory chips are made into memory modules (commonly called DIMM) before it can be used in the PC. Memory module manufacturers normally assume the chips are good because they have been through all the tests at the chip manufacturer. All they do is to “bolt” the chips onto a small PC board. Therefore, their test is concentrated on assembly errors and gross failures. The bad sold-joint can cause shorts and opens. Mis-handling on the assembly line can cause static-discharge problem and dead cells. Functional cell test with standard test patterns is the best test for the process. Since the gross profit margin for the module assembler is low (at $0.25 to $0.50 per module), the amount of test time will distinguish profit from loss. Automatic memory handler is a must to further compensate the manual handling cost. Due to the low profit margin, module assemblers cannot afford the large ATE tester. Instead, they have chosen small functional testers specially made for memory module testing.

There is another class of memory module manufacturers, they are commonly known as “downgrade” module manufacturers. These manufacturers do not use the DRAM from the regular channel. Instead they start out with wafers that have only completed the DC parametric test at the DRAM manufacturers. These wafers are color die marked for bad and partially bad chips. At this stage, these chips are not functional tested nor burnt-in.

In order to save cost, these wafers are sent directly for packaging and module assembly. Since these chips are rather raw, the assembled modules will have to go through more stringent tests than the normal module. In downgrade module manufacturing, usually two test processes are applied. The first test is functional testing to screen out assembly shorts and opens.

This is very similar to the regular module assembly test. However, the difference is in the second test. The second test is the motherboard burn-in test using live motherboards. Downgrade module manufacturers usually have racks and arrays of motherboards in their test room. The motherboards are normally fully populated with memory modules filling all available memory slots. “Motherboard boot test” and “system memory diagnostic test” are applied. 24 to 72 hours motherboard test are usually used to offset the burn-in test normally done at the chip manufacturer. However, the drawback for the motherboard test is the short socket life span and the lack of faulty chip pinpoint mechanism.

Dealers and Computer Service Test

Computer integrator and memory module retailer need a reliable tool to quickly verify their memories in front of their customer. They need a tester that is easy to understand and to use. Most of all, it has to gain their customer’s trust.

On the other hand, the corporate computer service department would have a different scenario. The corporate networking technicians often run into secretaries that have bad or intermittent computer. A diagnostic memory test is required to quickly isolate the memory fault from the CPU fault.

The same small functional memory DIMM tester used by the memory module manufacturers usually fills the above two requirements very well. It is portable, quick, and easy enough to be used by sub-technical personnel. The difference in this application is that no robotic loading is required. Without the mechanical loading option, the low cost of the tester justifies for the mission.

The End User Test

The end user usually would not afford a functional memory tester. Yet, the memory problems that border them are the “blue screen” and “memory parity” errors. These errors would not inhibit the PC booting process but will cause the program to hang during operation. The test they use would be memory diagnostic software. The two most popular software available to analyze hidden problems in PC memory would be “Ram Stress” from RST and “DocMemory” from www.simmtester.com

The memory diagnostic software exercises the entire PC memory in different test patterns to uncover all the soft-errors. They can usually pick up the bad cell and pinpoint to the data bit and the module. However, the disadvantage is the slow test time (usually tens of minutes) and can only be used on a booted up computer. Besides, memory diagnostic software cannot guarantee the memory will work in another computer other than the one performed the test.

In Summary

1. Million dollars ATE testers and handlers are used at chip level testing.
2. Low cost functional testers and motherboard tests are used at module manufacturing.
3. The dealer and service technicians would prefer a portable functional tester.
4. End users are likely to use PC memory diagnostic test to isolate the fraud.

Test Cost comparison

Test cost is proportional to how much test pattern you want to use. Of which “test time” is the most expensive.

Notes: Assuming standard test patterns applied.
Test labor and overhead not included.


The capital amortization in DRAM testing is still relatively small in comparison with the chip price and the module cost. That is as long as the manufacturers are keeping up with their process yield, small geometry, large wafer, and high-density chips to fetch over $30 a module.

On the other hand, memory manufacturers have to watch out on their test labor cost. High throughput in testing will greatly reduce test labor and test cost. That would allow the memory manufacturers to survive even in the era of price-market fluctuation.

By: DocMemory
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