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DDR MEMORY—What is it ? How to test it ?
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Monday, January 29, 2001
Introduction
In the last few years, CPU speeds has accelerated exponentially. Yet, computer memory speed has not matched to the expectations. We saw the mass migration from PC100 memory to PC133 memory in 1999. During the time, Intel also introduced Rambus memory as a new memory solution to the PC industry. In the transition, each memory technology promises more bandwidth and performance. In theory, higher memory bandwidth will deliver better performance for the computer system. Memory peak bandwidth is defined as memory bus width/8 bits x data rate. That translates into how fast your 3D games will react, how smooth your MP3 music will play or how good a motion picture you can play in your MPEG video streaming.
This year, a new type of memory called DDR has shown up in the new PC’s. Although it is a mystery to most users, it is the result of more than three years of engineering work at an industry collaboration involving hundreds of top memory and system design engineers. This new kind of DDR memory is promising yet more memory bandwidth and performance. But best of all, it is at lower prices in comparison to Rambus memory.
Bandwidth calculation: memory bus width/8 bits x data rate.
PEAK MEMORY BANDWIDTH CHART
What is DDR?
DDR is an abbreviation for "Double Data Rate". DDR is indeed very similar to the normal Synchronous DRAM. The normal Synchronous DRAM (we now called SDR) was evolved out of the standard DRAM.
The standard DRAM receives its address command in two address words. It is a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the Row Address Strobe (RAS). Following the RAS command is the Column Address Strobe (CAS) for latching the second address word. Shortly after the Ras and Cas strobes, the stored data is valid for reading.
The SDR DRAM combines a clock with the standard DRAM. The Ras, Cas, and also Data valid are enabled on the rising edge of each clock cycle. Due to the clocking, the position of the data and the rest of the signals are now very predictable. Thus that data latch strobes can be positioned very precisely. Since the data valid window is very predictable, the memory can now be divided into four banks to allow internal cell pre-charge and pre-fetch. Burst mode is also added to allow consecutive address fetching without repeating the Ras strobe. Continuous Cas strobe would bring out consecutive data as long as they are from the same Row.
DDR memory works very similar to the SDR except that data is read at both leading edge and falling edge of the clock. Thus a single frequency clock can result in a data transfer as fast as twice the frequency of the clock. The new generation of DDR memory is running at 200Mhz and 266Mhz data rate corresponding to clock frequencies of 100MHz and 133MHz.
WAVEFORM DIAGRAM COMPARING SDRAM, SDR AND DDR.
How to Test DDR?
Although DDR memory is similar to SDR, the doubling of the data frequency does present a new challenge to the test engineer. The tester does not only have to latch the data read at twice the frequency but also have to provide the write data at twice the speed. There are two areas of DDR testing that leads to separate test requirements :
Chip-Level testing
DDR chips are tested at the wafer probe level and also at the final package level. The tester used is usually rated as the ATE memory tester. This kind of tester usually cost several million dollars and is constructed as a fine time resolution (100ps – 1ns step) programmable signal generator. The test engineer can program the tester to simulate the actual operational environment. He can also tweak the timing edges back-and-forth to find the “fall-off” point.
ATE test systems do have a drawback. The amount of arbitrary waveform it can generate is limited by its backup memory “Shadow Ram”, and its algorithm generator. Depending on its depth of “Shadow Ram”, the waveform have to repeat its own cycle. Since DDR has twice the speed and bandwidth of the normal SDR, the waveform generation will require twice as many transitions. The “Shadow Ram” on the same tester is, therefore, quickly consumed. Test engineers found that they have to either upgrade their testers for more memory or stand the chance of compromising test resolutions.
Test head building can be a complex issue, too. Since the data read window of the DDR memory is only 1-2ns, pin driver rise and fall time becomes critical. Better slew rate is required on the pin drivers to ensure the signal transition will be at the center of the data eye.
Transmission line reflection gets into play at 266MHz. Test engineers found that they have to follow straighter rules in designing their test platforms. Transmission line simulations have to be done on their test head layout to ensure signal integrity. Pin driver strength also has to be scalable to minimize high frequency signal reflections.
Signal integrity analysis have to be done in simulations to assure signals fall within the good data “eye”
TEST HEAD DESIGN SIMULATIONS
DFT is preferred but not adopted. Since test-time and cost on an ATE test system is proportional to the number of megabits on the memory chip, it becomes very costly in testing larger DDR chips. There has been push on universal Design-For-Test (DFT) features with the new DDR chips. It attempts to incorporate internal nodes that are sufficiently controllable and observable. Specific DFT techniques include providing parallel test modes to test multiple arrays simultaneously were proposed at JEDEC, the industry standard committee. Unfortunately, it was not adopted due to the extreme consciousness on chip die size. DDR was viewed as a commodity that has to have minimum die size for price competition.
Memory Module Testing
When comes to memory module testing, the requirements are different. The DDR module manufacturers assume that the DDR had been tested for semi-conductor failures at the chips level. Their test is, therefore, concentrated on functional exercise and assembly errors. With the new DDR DIMM (dual in-line memory module) and SODIMM (small outline dual in-line memory module), we will likely to see three different approaches on memory module testers:
The two passes read DDR testing. This is probably the easiest tester to build. Most tester companies would make slight modification on their existing SDR tester to come up with this quick-to-market DDR tester. In the write mode, an SDR tester would write identical data onto two consecutive bits of a DDR memory. In the read back, the SDR tester can first read the odd bit data (every other bit) from the DDR module. It then ran on a second pass to read the even bits by shifting the data latch by half a clock period. This will essentially allow the tester to completely access all the DDR memory cells. This kind of test method can not include true burst test and is not a real cycle time test.
Tester utilizing a real time controller. It is not difficult to design a DDR tester utilizing a real time ASIC controller. After all, new ASIC blocks have demonstrated that they can reach the required frequency of 266MHz easily. However, due to the volume of testers and the price competitive market, Field Programmable Gate Array (FPGA) is the preferred logic core for cost/volume justifications.
Building a 266MHz memory controller on a FPGA is a challenge because it will take the latest 0.18 micron line width chip to achieve the performance. Even though the 0.18 micron chips are available, yet the synthesizing programs are not yet fully debugged. Close working relationship with FPGA vendors is necessary to overcome all the huddles.
This kind of tester will not only be at low cost, it also brings test speed and test accuracy.
The “Native Environment” tester. Regardless of all the other test methods, memory module manufacturers are always looking for the ultimate “motherboard simulator”. They believe the best test would be done on the actual motherboard under the actual operational environment. However, the manufacturers also know that there are inherent problems on the PC motherboard that prohibits it to be used as a tester. The problems are attributed to slow boot time, slow test execution time and also relative short life of the memory module sockets.
Through technological breakthroughs, these problems can be overcome with special hardware and software design. New “Native Environment” DDR module testers will be introduced. They will be built with X86 processors and PC chipsets. These testers will take away the slow boot time by implementing special test operational systems. It will also utilize a combination of cache execution with special software algorithm to time-out the DIMM sockets. That means you can now change the DUT (device under test) module without having to physically power down and reboot the system. Well, of course, the tester will not be come in the form of a motherboard. Instead, it will be layout like a tester with optimized convenience of a tester. It will also have heavy duty test socket for heavy cycle of insertion durability.
DDR DIMM Module Test Handling
But most of all, a good memory module tester needs a compatible automatic handler to complete the production solution. Conventionally, memory module handler uses gold finger contactor to make electrical probe contact with the memory module connection taps. At the 266MHz DDR frequency, the 2 inches long contactors would degrade the signal to a point of measurement error. A new class of handler using “direct socket” testing has come into the market to fill the needs. This kind of automatic memory module handler uses the normal test socket found in manual testing. The handler gently punches the module under test into the test socket simulating the normal hand insertion action. The module is then tested and gently withdrawn from the test socket.
CST DIRECT SOCKET INSERTION ROBOFLEX HANDLER
Conclusion
The DDR test transformation is evolutionary instead of revolutionary. JEDEC (the industry standard setting committee) is not standing still on this technology. Instead, it has a road map on further development of DDR memory. In the path will be DDR333 for the 2002 time frame and then DDRII for the year of 2004. Physical package will also be migrating from TSOPII (thin small outline plastic package) to FBGA (flip-chip ball grid array). Memory test engineers will continue to find challenge and work through these changes.
By: Cecil Ho/ CST Marketing
Copyright © 2023 CST, Inc. All Rights Reserved
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