Thursday, April 30, 2026
Korean memory manufacturer SK hynix has announced a yield improvement for its hybrid bonding packaging technology for high bandwidth memory (HBM) modules. Hybrid bonding enables memory chip manufacturers to bond memory layers with each other without relying on bumps. The direct contact enables higher speeds and improved efficiency through lower heat generation. SK Hynix's technical leader, Kim Jong-hoon, revealed the development at the Beyond HBM — Core Technologies of Advanced Packaging: From Next-Generation Substrates to Modules conference in South Korea, reports The Elec.
Latest Packaging Technology To Come Into Play With Next-Generation HBM 4 Memory Chips
High bandwidth memory is assembled by stacking several memory dies on top of each other and then assembling the final package. Stacking these dies typically requires connecting them through bumps, and currently, memory chips typically see 8/12 layers stacked on top of each other.
However, to improve speed, performance and capacity, next generation memory modules, such as HBM4 and HBM5, require more layers. At the same time, the package size has to be maintained as well in order to cater to space constraints. As a result, hybrid bonding enables memory manufacturers to stack more layers into a similarly sized package by removing the bumps that connect the memory dies.
SK hynix Will Continue Advanced Underfill Technique Until Hybrid Bonding is Available
Before it starts producing memory chips with hybrid bonding, SK hynix aims to continue to utilize its Mass Reflow-Molded Underfill (MR-MUF) technology. Like hybrid bonding, MR-MUF also aims to reduce the gap between the memory dies, but, unlike hybrid bonding, it continues to use copper bumps. However, the technology relies on heating the stack as a whole and then filling the gaps between the dies with an underfill.
While HBM memory chips are typically considered in the context of enterprise computing and workloads, hybrid bonding can create advantages for consumers as well through performance improvement. At the same time, the chips are likely to be expensive and in short supply as constraints remain due to high demand from the data center market.
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