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TSMC Launches A13 Process and Advanced Technologies
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Tuesday, April 28, 2026
Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) introduced its A13 process technology at its 2026 North America Technology Symposium, positioning it as a direct shrink of the previously announced A14 node to support increasing computational demands across artificial intelligence (AI), high-performance computing (HPC), and mobile applications.
A13 delivers 6% area reduction compared with A14 and maintains full backward compatibility with A14 design rules, enabling faster customer migration to the company’s nanosheet transistor architecture. The process also provides improved power efficiency and performance through design-technology co-optimization and is scheduled for production in 2029, one year after A14.
The announcement was made at the symposium held in Santa Clara, which carries the theme “Expanding AI with Leadership Silicon” and serves as TSMC’s primary annual customer event.
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“At TSMC, we understand our customers are always looking ahead to their next innovation and they come to us for a reliable stream of new silicon technologies, like A13, meticulously engineered to be ready for high-volume production right when their visionary new designs demand them,” said TSMC Chairman and CEO Dr. C.C. Wei. “TSMC’s advanced process technologies lead the industry in density, performance and power efficiency, and we continually strive to make them even better for our customers’ future products, ensuring customers’ success as their most reliable technological partner.”
Advanced logic and 2nm platform developments
TSMC also previewed A12, an enhancement of the A14 platform featuring Super Power Rail technology for backside power delivery in AI and HPC applications, with production targeted for 2029.
The company further advanced its 2nm roadmap with N2U, which delivers 3–4% speed improvement or 8–10% power reduction and a 1.02–1.03× logic density increase over N2P. N2U is scheduled for production in 2028.
3DFabric and packaging innovations
To address AI-driven demand for higher compute density, TSMC expanded its CoWoS® advanced packaging technology. The company is producing 5.5-reticle CoWoS and developing a 14-reticle version capable of integrating approximately 10 compute dies and 20 high-bandwidth memory stacks, targeted for production in 2028, with further scaling planned in 2029. These developments complement the 40-reticle SoW-X System-on-Wafer platform expected in 2029.
TSMC also introduced updates to its TSMC-SoIC® 3D stacking technology, with A14-to-A14 SoIC planned for 2029, delivering 1.8× higher die-to-die I/O density than N2-on-N2 SoIC.
In photonics, the company’s TSMC-COUPE™ technology will enable co-packaged optics production starting in 2026. By integrating optical engines within the package, it achieves 2× power efficiency and 10× latency reduction compared with pluggable solutions, demonstrated in a 200Gbps micro-ring modulator.
Automotive, robotics, and specialty technologies
For automotive and physical AI applications, TSMC announced N2A, its first automotive-grade nanosheet transistor process. N2A offers 15–20% speed gains at the same power versus N3A and is expected to complete AEC-Q100 qualification in 2028. The company is also enabling earlier automotive design through “Auto-Use” kits within its N2P process design kit.
N3A is set to enter production in 2026, with more than 10 automotive products planned under the N3 “Auto Early” program.
In specialty technologies, TSMC introduced its N16HV high-voltage FinFET process for display driver applications. Compared with N28HV, N16HV increases gate density by 41% and reduces power consumption by 35% for smartphone displays, while enabling over 20% power reduction and 40% die size shrink for near-eye display applications.
By: DocMemory
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