At the company’s North American Technology Symposium, Kevin Zhang, TSMC’s SVP for Business Development and Overseas Operations Office, and Deputy Co-COO, called it “the last and best finfet node.”

“The last and best finfet node”TSMC’s strategy is to develop multiple variants of the N3 process creating a comprehensive customisable silicon resource. “Our goal is to make integrated silicon performance a platform,” said Zhang.

As of now, the N3 variants either available or planned, are:

N3B: The baseline 3nm process.

N3E: a cost-optimised version with fewer EUV layers and no EUV double patterning. It offers lower logic density than N3 but with better yields.

N3P: An enhanced version of N3E, providing 5% higher performance or 5–10% lower power at the same speed, plus a 4% increase in transistor density for mixed designs.

N3X: Targeted at HPC, it allows for higher voltages and maximum clock frequencies. It offers 5% more speed than N3P at 1.2V.

N3S: A high-density variant aimed at maximising transistor density, potentially using single-fin libraries and possibly adopting backside power delivery.

N3RF: for RF products

N3A: for automotive products

N3C: for value-tier products

By: DocMemory
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