Monday, April 05, 2010
Determine Endurance on a NAND Flash Chip
What is “endurance” on a NAND Flash chip? The answer can be vague and inconclusive. Generally, the ballpark number on an SLC device (Single Level Cell) is 100,000 cycles while for MLC (Multi-Level Cell) is 10,000 cycles. To grasp the real picture, we should first look into the functional physic behind the NAND device and also understand how does it work?
What is a NAND Memory?
Let’s look at a simple FET transistor with Gate, Drain and Source. When a voltage (Vt) is applied to the Gate, the Gate is charged. At a certain point, electron moves down to the Drain/Source level to bridge the Drain and Source. The transistor is switched on. Drain and Source will conduct. We call this a “1” output.
A NAND Flash transistor adds Floating Gate between the regular Gate and the Dain/Source. This Floating Gate retards the electron migration and thus changes the threshold voltage (Vt) the transistor would turn on. Programming the NAND means injecting electrons to the Floating Gate. High Threshold voltage pulls electrons up and electron quantum-mechanically tunneling through the “tunnel oxide” to form a “0”. Erase means removing electrons from the Floating Gate and tunnel in reverse direct. The gate would be stuck on as a “1”.
One program followed by an erase is call a “cycle”. As NAND is used, it can undergo many cycles. During these cycles, the transistor exerts harsh stress on the tunnel oxide with very high electric field. Al lot of electrons passes through the oxide. As a result, the oxide degrades. Atomic bonds in the oxide can be broken, both in the bulk and at the interface. Broken –bond sites can trap electrons that pass through, becoming electrically negative. Tunnel oxide degradation is the main reason why the number of cycles possible (or endurance) is finite.
When negative charges in tunnel oxide raises the Vt so programming gets faster and erase slower with cycling. When a block erases slower than datasheet, it fails and is retired. NAND datasheet allow 2% to 4% of blocks to fail in this way. When that % is reached, the device itself has failed.
NAND Programming Structure
To simplify control architecture (see NAND architecture diagram), NAND program is in “page” unit, erase is in “block” uni