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Monday, October 20, 2014
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Understanding DDR Serial Presence Detect (SPD) Table


Monday, July 14, 2003

Understanding DDR Serial Presence Detect (SPD) Table

By: DocMemory

Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with "Turbo-Tax" type of multiple choices questions. I hope you will fin the information here interesting and useful.

Byte 0

Number of Serial PD Bytes written during module production

The most common for standard 184pin DIMM and 200pin SODIMM is 128 bytes written although some special modules and manufacturer would occasionally insert different number.

128 Byte 80h 255 Byte FFh

Byte 1

Total number of Bytes in Serial PD device

This is referring to the EEPROM size used. For standard 184pin DIMM and 200pin SODIMM, device used is usually 128 Bytes or 256 Bytes with 256 Bytes as the most common.

256 Byte (24C02) 08h 128 Byte (24C01) 07h

Byte 2

Fundamental Memory Type

This refers to the DRAM type. The most common now-a-days are either SDRAM or DDR. In this case, we are only dealing with DDR

DDR 07h recommended default

Byte 3

Number of Row Addresses on this assembly

This relates to the DRAM size as well as the Refresh scheme of the DRAM. The best way to discover this is to use the AutoID function of the CST DIMM tester. You would first run the AutoID on the tester. You then use the [Edit] [AdrDat] function to display the Row and Column Address counts.

13 0Dh 12 0Ch 11 0Bh 10 0Ah 9 09h

Byte 4

Number of Column Addresses on this assembly

This relates to the DRAM size as well as the Refresh scheme of the DRAM. The best way to discover this is to use the AutoID function of the CST DIMM tester. You would first run the AutoID on the tester. You then use the [Edit] [AdrDat] function to display the Row and Column Address counts.

13 0Dh 12 0Ch 11 0Bh 10 0Ah 9 09h

Byte 5

Number of Physical Banks on DIMM

This is referring to the internal banks (or ranks) on the module. Normally, you can count the number of chips on the module and make a guest that there would be one bank (rank) for each 8 pieces of DRAM chips. However, downgrade modules often use two defective chips to replace one. Stacked modules also uses two chip stacked as one physical chip. Those would make the identification very complex. The best way to identify the banks (ranks) would be to use the AutoID function in the CST testers. The tester displays number of internal Banks directly after AutoID is executed.

1 B 01h 2B 02h 3B 03h 4B 04h

Byte 6

Module Width of this assembly

This refers to the number of data bit width on the module. For a standard 8 byte DIMM, 64 bits would be most common while an 8 byte ECC module would have 72 bits. Some special module might even have up to 144 bits. In any case, a CST tester AutoID function would tell you this number in plan English.

64 bit 40h 72 bit 48h 144bit 90h

Byte 7

Module width of this assembly (Continue)

This byte is used only if your DIMM exceeds 16 bytes (144 bits).

  1. additional bit 00h recommended default

    Byte 8

    Voltage Interface Level of this assembly

    This refers to the power supply voltage Vdd of the DIMM. Standard DDR module would be 2.5V SSTL

  2. 2.5V DDR 04h recommended default

Byte 9

SDRAM Device Cycle time at Maximum Supported CAS Latency

This commonly referred to the clock frequency of the DIMM. Running at its specified CL latency.

266MHz data rate DDR 75h 333MHz data rate DDR 60h 400MHz data rate DDR 50h 433MHz data rate DDR 46h 466MHz data rate DDR 42h

Byte 10

SDRAM Device Access from Clock (tAC)

This is referred to the data valid time from the clock. This can be read directly from the DRAM manufacturer data sheet. But caution must be taken to read off the correct column since this is CL (clock latency) related. In the DDR data sheet, it is listed as tAC and is in fraction of a nano-second (ns).

+/-0.6 ns 60h +/-0.65 ns 65h +/- 0.7 ns 70h +/-0.75 ns 75h

Byte 11

DIMM Configuration Type

This is to identify the DIMM as ECC, Parity, or Non-parity. Normally non-parity is related to 64 bit module, Parity and ECC are related to 72 bit or higher memory bit width on the module.

Non ECC 00h ECC 02h

Byte 12

Refresh Rate/Type

This byte describes the module’s refresh rate and if it is self-refreshing or non-self refreshing. Today, most standard modules would be capable of self-refreshing. The refresh time is easily read from the DRAM manufacturer data sheet. Refresh time can be listed in two different ways.

1. In Refresh Interval Time. For example: 15.6usec. or 7.8usec.

2. In milli-seconds per x Refresh Cycles. For example: 62.4ms in 8K refresh cycles.

This can be converted back into refresh interval time with the equation:

Refresh Interval = Total Refresh Period / number of refresh cycles

15.6 usec. Self-refresh (4K) 80h 7.8 usec. Self-refresh (8K) 82h

Byte 13

Primary SDRAM Width

This refers to the bit width of the DDR DRAM.

For a standard DIMM module. 4 bits 04h 8 bits 08h 16 bits 10h

Byte 14

Error Checking SDRAM Width

This refers to the bit width of the error checking DRAM. For a standard module, it is either no ECC bit, 8 bits, or 16 bits on a 144 bit module.

0 bit 00h 8 bits 08h 16bits 10h

Byte 15

Minimum Clock Delay, Back-to-Back Random Column Access (tCCD min).

This is read off the tCCD min column of the DRAM data sheet and is in the unit of clock cycles. For the most case, it is 1 clock cycle.

1 clock cycle 01h 2 clock cycle 02h

Byte 16

Burst Lengths Supported

This is indicates the burst length supported. In most case, it is 2,4,8 burst supported.

2, 4,8 Burst length supported 0Eh recommended default

Byte 17

Number of Banks on SDRAM Device

This is referring to the internal bank on the DRAM chip. All modern DDR have 4 internal banks.

4 Internal Banks 04h recommended default

Byte 18

CAS Latency (CL)

This refers to the all the different Cas Latency supported by your chip. This can vary with the frequency you operate your DIMM. This number can be read off your DRAM data sheet.

CL=2.5 and 3 supported 18h

CL=2.0, 2.5 and 3 are all supported 1Ch

Byte 19

Chip Select Latency

This is the maximum time between the activation of CS to the time the Chip Select is effective. This is counted in number of clock cycles. For modern DRAM, this number is 0 clock cycle.

0 clock cycle 01h recommended default

Byte 20

Write Latency

This is the maximum time between the activation of WE to the time that writing is effective. This is counted in number of clock cycles. For most modern DDR SDRAM, this number is 1 clock cycle.

1 clock cycle 02h recommended default

Byte 21

SDRAM Module Attributes

This byte describes the DIMM, whether it is unbuffered, registered, differential clocked or with FET switches.

Unbuffer DDR DIMM with differential clock 20h

Registered DDR DIMM 26h

Byte 22

SDRAM Device Attributes

This byte describes the DRAM specification on voltage tolerance, the type of pre-charge supported, plus support of dual strength drivers. Modern DRAM are standardized on these features. These features are usually found on the feature list of the DRAM specification sheet.

DDR (Fast AP, Concurrent AP supported) C0h recommended default

Byte 23

SDRAM Minimum Clock Cycle Time Derated by Half a Clock

This is referred to the speed the DRAM can run at when the Cas Latency is reduced by 0.5 clock. This data can be looked up from the datasheet of the DRAM. This is usually listed at the first page of the data sheet where it mentioned highest frequency it can run at a certain cas latency setting.

With 0.5 CL derate, it would work as a DDR200 A0h

With 0.5 CL derate, it would work as a DDR266 75h

With 0.5 CL derate, it would work as a DDR333 60h

Derated operation not allowed 00h

Byte 24

Data Access Time from clock when CL is Derated by Half a Clock (derated tAC)

This is referred to the tAC (access time) the DRAM can run at when the Cas Latency is reduced by 0.5 clock. This data can be looked up from the datasheet of the DRAM. This is usually listed at the first page of the data sheet where it mention maximum frequency it can run at a certain cas latency setting.

+/-0.65 ns 65h +/- 0.7 ns 70h +/-0.75 ns 75h

Derated operation not allowed 00h

Byte 25

SDRAM Minimum Clock Cycle when CL is Derated by One Clock

This is referred to the speed the DRAM can run at when the Cas Latency is forced to reduce by two notches. (that is 1 clock for DDR) This data can be looked up from the datasheet of the DRAM. This is usually listed at the first page of the data sheet where it mentioned what frequency it can run at a certain cas latency setting.

DDR 400 CL3 cannot be degraded to lower than CL2.5 as listed in Byte 18 00h

With 1 CL derate, it would work as a DDR200 A0h

With 1 CL derate, it would work as a DDR266 75h

With 1 CL derate, it would work as a DDR333 60h

Derated operation not allowed 00h

Byte 26

Data Access Time from clock when CL is Derated by One Clock. (derated tAC)

This is referred to the tAC (access time) the DRAM can run at when the Cas Latency is derated by 1 clock. This data can be looked up from the datasheet of the DRAM. This is usually listed at the first page of the data sheet where it mentions the maximum frequency it can run at a certain cas latency setting.

+/-0.65 ns 65h +/- 0.7 ns 70h +/-0.75 ns 75h

Derated operation not allowed 00h

 

Byte 27

Minimum Row Pre-charge Time (tRP)

This is tRP read off the DRAM data sheet.

12ns 30h 15ns 3Ch 18ns 48h 20ns 50h

Byte 28

Minimum Row to Row Access Delay (tRRD)

This is the tRRD time read off the DRAM data sheet

10ns 28h 12ns 30h 15ns 3Ch

Byte 29

Minimum Ras to Cas Delay (tRCD)

This is the tRCD time read off the DRAM data sheet.

12ns 30h 15ns 3Ch 18ns 48h 20ns 50h

Byte 30

Minimum Active to Pre-charge Time (tRAS)

This is the tRAS time read off the DRAM data sheet.

40ns 28h 45ns 2Dh 50ns 32h 55ns 37h

Byte 31

Module Bank Density

This refers to the Mega-Byte in each physical bank (rank) on the DIMM. For example: if a 256MB module has two physical banks, then each physical bank should have 128MB.

32 MB 08h 64MB 10h 128MB 20h 256MB 40h 512MB 80h

Byte 32

Address and Command Input Setup Time Before Clock (tIS)

This refers to the time of the address and command lines have to occur before the next clock edge. It is labeled as tIS in the case of DDR.

(tIS) 0.6ns. 60h 0.8ns 80h 1.0ns. A0h

Byte 33

Address and Command Input Hold Time After Clock (tIH)

This refers to the period of time the address and command lines have to hold after the last clock edge has appeared. It is labeled as tSH in SDRAM and tIH in the case of DDR.

(tIH) 0.4ns. 40h 0.6ns. 60h 0.8ns. 80h 1.0ns. A0h

Byte 34

SDRAM Device Data/Data Mask Input setup Time Before Data Strobe (tDS)

This refers to the time of the Data and Data Mask lines have to occur before the next clock edge. It is labeled as tDS in the case of DDR.

(tDS) 0.4ns. 40h 0.6ns 60h 0.8ns. 80h

Byte 35

Address and Command Input Hold Time After Clock (tDH)

This refers to the period of time the Data and Data Mask lines have to hold after the last clock edge has appeared. It is labeled as tDH in the case of DDR.

(tDH) 0.4ns. 40h 0.6ns. 60h 0.8ns. 80h 1.0ns. A0h

Byte 36-40

Reserved for Virtual Channel SDRAM

Normally Not VC SDRAM 00h

Byte 41

Minimum Active to Active Auto Refresh Time (tRC)

55ns 37h 60ns 3Ch 65ns 41h 70ns 46h

Byte 42

Minimum Auto Refresh to Active Auto Refresh Time (tRFC)

70ns 46h 75ns 4Bh

Byte 43

Maximum Device Cycle time (tCKmax)

10ns 28h 12ns 30h

Byte 44

Maximum Skew Between DQS and DQ (tDQSQ)

Maximum DQS tolerance

0.4ns 28h 0.5ns 32h 0.6ns 3Ch

Byte 45

Maximum Read DataHold Skew Factor (tQHS)

Maximum DQS and DQ window tolerance.

0.5ns 32h 0.6ns 3Ch

Byte 46

PLL Relock Time

Not available 00h recommended default

Byte 47-61

Superset Information

Not available 00h recommended default

Byte 62

SPD Data Revision Code

Revision 0.0 00h Revision 1.0 10h Revision 2.0 20h

Byte 63

Checksum for Byte 0 to 62

Checksum is calculated and placed into this byte. All CST testers have automatic checksum calculation for this byte. All you have to do is to fill in and audit byte 0-62, the tester will automatically fill in byte 63 for you through the auto-checksum calculation.

Byte 64-71

Manufacturer’s JEDEC ID Code

This is a code obtained through manufacturer’s registration with JEDEC ( the standard setting committee). A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office.

Byte 64 is the most significant byte. If the ID is not larger then one byte (in hex), byte 65-71 should be filled with 00h.

Byte 72

Module manufacturing Location

Optional manufacturer assigned code.

Byte 73-90

Module Part Number

Optional manufacturer assigned part number.

The manufacturer’s part number is written in ASCII format within these bytes. Byte 73 is the most significant digit in ASCII while byte 90 is the least significant digit in ASCII. Unused digits are coded as ASCII blanks (20h).

Byte 91-92

Module Revision Code

Optional manufacturer assigned code.

Byte 93-94

Module Manufacturing Date

Byte 93 is the year: 2002 66h 2003 67h 2004 68h

Byte 94 is the week of the year: wk1-wk15 01h – 0Fh

wk16-wk31 10h – 1Fh

wk32-wk47 20h – 2Fh

wk48-wk52 30h – 34h

Byte 95-98

Module Serial Number

Optional manufacturer assigned number.

On the serial number setting, JEDEC has no specification on the data format nor dictates the location of Most Significant Bit. Therefore, it’s up to individual manufacturer to assign his numbering system. All CST testers and EZ-SPD programmers have the option for user to select either byte 95 or byte 98 as the MSB (most significant bit). The testers assume the use of ASCII format; which is the most commonly used. The CST testers also have the function to automatically increment the serial number on each module tested.

Byte 98-127

Manufacturer’s Specific Data

Optional manufacturer assigned data.

Byte 128-255

Open for Customer Use

Optional for any information codes.

 


Final Note:

Everything in the above article and more are now implemented into the CST EZ-SPD DDR Programmer software. The new features are:

1. Pop up window of explanation on each Byte.

2. Clickable selection right from the illustration window.

3. Auto checksum on byte 62.

4. Text input on "manufacturer code" and "serial number". User define MSB/LSB format.

5. Auto JEDEC week and year coding from PC clock.

6. Software write protect function.

.....just to name a few.

For further information, please check this link  : http://www.simmtester.com/page/products/ezspd/spdinfo.asp


By: DocMemory
Copyright © 2003 CST, Inc. All Rights Reserved

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