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Friday, June 22, 2018
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Understanding DDR4 Serial Presence Detect (SPD) Table


Monday, November 25, 2013

DDR4 SPD Definition

Understanding DDR4 Serial Presence Detect (SPD) Table

By: DocMemory

Introduction

Since I wrote “Understanding DDR Serial Presence Detect (SPD) Table” in 2003, I have been getting a lot a feedback from readers. I added “Understanding DDR2 Serial Presence Detect (SPD) Table” in 2006. Some of you told me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses.

In 2007, I continued to add “Understanding DDR3 Serial Presence Detect (SPD) Table” to the series. Reader feedback was once again very positive.





















Lately, CST has started shipment of a DDR4 EZ Programmer. Since the DD4 DIMM is introduced recently, I think this is the time to add an article for the DDR4 SPD Table. Due to the many more years of development, the DD4 SPD table has definitely gotten more sophisticated than the original DDR, DDR2 and DDR3 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to accommodate you all.

Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with “Turbo-Tax” type of multiple choices questions. I hope you’ll find it interesting and useful.

Byte 0

Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage

Bit 3 to Bit 0 describes the total size of the serial memory actually used in the EEprom for the Serial Presence Detect data. Bit 6 to Bit 4 describes the number of bytes available in the EEprom device, usually 128byte or 256 byte. On top of that, Bit 7 indicates whether the unique module identifier covered by the CRC encoded on bytes 126 and 127 is based on (0-116byte) or based on (0-125byte)..

(When CST EZ-SPD Programmer is used: Simply select items from 3 tables and automatically calculate the final hex number)

The most common one used is:

Total SPD Bye = 512
CRC Coverage = 0-125Byte
SPD Byte used = 384 Byte
Resulting code is 23h

Byte 1

SPD Revision

Version 0.0    00h
Revision 0.7    07h
Revision 0.8    08h
Revision 0.9    09h
Revision 1.0    10h
Revision 1.1    11h
Revision 1.2    12h

Byte 2

DRAM Device Type
This refers to the DRAM type. In this case, we are only dealing with DDR4 SDRAM.
DDR4 SDRAM: 0Ch

Byte 3

Module Type
This relates to the physical size, and category of memory module.
Undefined 00h
RDIMM (Registered Long DIMM) 01h
UDIMM (Unbuffered Long DIMM) 02h
SODIMM (Small Outline DIMM) 03h
LRDIMM (Small Outline DIMM) 04h

Byte 4

SDRAM Density and Banks
This byte defines the total density of the DDR4 SDRAM, in bits, and the number of internal banks into which the memory array is divided.

Presently all DDR4 have 8 internal banks.

SDRAM Chip Size 

4 Bank Groups 8 Internal Banks 4Gb 94h
4 Bank Groups 8 Internal Banks 8Gb 95h
2 Bank Groups (X16 chip) 8 Internal Banks 4Gb 54h
2 Bank Groups (X16 chip) 8 Internal Banks 8Gb 55h

Byte 5

SDRAM Addressing

This byte describes the row addressing and column addressing in the SDRAM Device.

4Gb chips 

1GbX4 16 Row X 10 Column 21h
512MbX8 15 Row X 10 Column 19h
256MbX16 15 Row X 10 Column 19h

8Gb chips 

2GbX4 17 Row X 10 Column 29h
1GbX8 16 Row X 10 Column 21h
512MbX16 16 Row X 10 Column 21h

Byte 6

This byte describes the type of SDRAM Device on the module.

Monolithic single die DRAM 00h
Non-monolithic 2 die multi load stack 91h
Non-monolithic 4 die multi load stack A1h
Non-monolithic 8 die multi load stack B1h

Non-monolithic 2 die 3D stack 92h
Non-monolithic 4 die 3D stack A2h
Non-monolithic 8 die 3D stack B2h

Byte 7

SDRAM Optional Features

This byte defines support for certain SDRAM features. This value comes from the DDR4 SDRAM data sheet.
(When CST EZ-SPD Programmer is used: Simply select the tMAW and the MAC. It automatically calculate final hex number for you)

Maximum Activate Window = tMAW
Maximum Ativate Count = tRRMAC
tMAW = 8192 * tREFI, with tRRMAC = 700K  01h
tMAW = 8192 * tREFI, with tRRMAC = 600K  02h
tMAW = 8192 * tREFI, with tRRMAC = 500K  03h
tMAW = 8192 * tREFI, with tRRMAC = 400K  04h
tMAW = 8192 * tREFI, with tRRMAC = 300K  05h
tMAW = 4096 * tREFI, with tRRMAC = 700K  11h
tMAW = 4096 * tREFI, with tRRMAC = 600K  12h
tMAW = 4096 * tREFI, with tRRMAC = 500K  13h
tMAW = 4096 * tREFI, with tRRMAC = 400K  14h
tMAW = 4096 * tREFI, with tRRMAC = 300K  15h
tMAW = 2048 * tREFI, with tRRMAC = 700K  21h
tMAW = 2048 * tREFI, with tRRMAC = 600K  22h
tMAW = 2048 * tREFI, with tRRMAC = 500K  23h
tMAW = 2048 * tREFI, with tRRMAC = 400K  24h
tMAW = 2048 * tREFI, with tRRMAC = 300K  25h
Optional Features Unknown  30h

Byte 8

SDRAM Thermal and Refresh Options
Reserved 00h

Byte 9

Reserved
Reserved 00h

Byte 10

Reserved
Reserved 00h

Byte 11

Module Nominal Voltage, VDD
This byte describes the voltage Level for DRAM and other components on the module such as the register or memory buffer if applicable. However, this excludes VDDSPD.
Normal DRAM VDD=1.2V only 03h
Normal DRAM VDD =1.2V, Can endures but not operate on VDD TBD1 0Bh

Byte 12

Module Organization
This byte describes the organization of the module.
(When CST EZ-SPD Programmer is used: Simply select number of Ranks and Device Width. It automatically calculate final hex number)
1 Rank module using X8 chips  01h
2 Rank module using X8 chips  09h
1 Rank module using X4 chips  00h
2 Rank module using X4 chips  08h
4 Rank module using X8 chips  19h
4 Rank module using X4chips  18h
1 Rank module using X16 chips  02h
2 Rank module using X16 chips  0Ah

Byte 13

Module Memory Bus Width
This refers to the primary bus width of the module plus the additional with provided by ECC
16bit 01h
32bit 02h
64bit (no parity) 03h
64bit + ECC (72bit) 0Bh

Byte 14

Module Thermal Sensor
This byte describes the module’s supported thermal options.
Use thermal sensor 80h
Does not use thermal sensor 00h

Byte 15

Reserved
Reserved 00h

Byte 16

Reserved
Reserved 00h

Byte 17

Time bases
This byte defines a value in picoseconds that represent s the fundamental timebase for fine grain and medium grain timing calculations. These values are used as a multiplier for formulating subsequent timing parameters.

Medium Timebase (MTB) of 125ps and Fine Tim