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Innovative Testing Puts Fallout DRAM Back Into Systems


Wednesday, January 29, 2003

Innovative Testing Puts Fallout DRAM Back Into Systems

DRAM manufacturers are always pushing for new generation. Presently, 256Mbit chips and 256MB DIMM are the most popular memory configurations. As recent as last summer, it was the 128Mbit and the 128MB that gained favor. However, each time the DRAM manufacturers introduce a new die, there is always some yield problem associate with it at the startup period. Whether it is a wafer outer parameter problem or just uneven sputter of chemicals, fallout chip accumulates until the process arrive maturity on that generation.

DRAM Wafer First Pass Test

The first pass test on a DRAM wafer is done by an ATE tester. This is a relatively large machine made especially for detail test of memories. This machine usually comes with a measurement head for DC parametric tests. This measurement head has the capability to measure small DC current as low as 10 microampere.

Due to the imperfection of the process, there is a percentage of the DRAM die that contains some faulty cells. Manufacturers improve their yield by applying a laser repair process. This process cuts away the known bad memory cells and replaces them with spare cells on the same die. In order to isolate the bad cells, manufacturers have to excite the entire memory array on the chip. That means every cell on the chip has to be exercised and tested. The test performed is normally called the "functional test".

Selected test patterns are written into each cell and read back in special sequence and order to verify their proper functionality. In order to reduce the test time, parallel chip testing are performed usually with 8 to 16 chips in a row.

The above test is performed at the wafer level with automatic die stepping probes. A special ink jet is also used to color mark the good dies. The wafer is then sent off for laser repair and to the backend for die separation and final packaging. Functional test is performed again at the post package level.

An Inked Die Don''''t Always Make It All-The-Way Through

A chip manufacturer has great concern about contaminants in the processing that would hide problems for the initial period of time. Burn-in test is usually used to weed out this infant mortality problem. Live burn-in is by putting the chips into a chamber under elevated temperature, usually at 50-70 degree C for 72 hours. In order to save time, elevated supply voltage is used to accelerate the aging process. During the test, signals are applied to the DRAM to keep them in the active state.

Depending on the maturity of the process and the design, some percentage chips usually fall out during the post burn-in functional test. These chips are proven to be out of the manufacturer''''''''s specifications. They either have bad cells or simple do not pass a certain pattern test. Since these chips are already in the final epoxy package, the DRAM manufacturers would sell it as "downgrade" or sometimes called the "C grade" chips. In order to protect the DRAM manufacturers'''''''' own image, these down grade transactions are usually kept in low profile with a precondition for the buyer to remark and not to expose the origin of the chips.

The Downgrade Memory Module Manufacturers

There is a class of memory module manufacturers, they are commonly known as "downgrade manufacturers". These manufacturers do not use the DRAM from the regular channel. Instead they buy "C grade" DRAM from regular memory chip manufacturers and produce what is generally termed as "OEM Memory Modules". Since these chips are known bad chips, they will have to first go through stringent tests and divided into different failure classifications. According to the classification and the test result, these chips are then assembled onto specially designed DIMM PC boards that can turn partially bad chips into a working memory module.

How Downgrade Chips Are Sorted?

"C grade" memory chips can be tested and classified into the following categories:

1. All bits functional.
2. Partial good with address line fault.
3. Partial good with data line fault.
4. Not functional

The objective is to find out which bits are good and usable. For example: a 32Mbx8 chip, might only be 4 bits bad. The rest of the 4 bits are still usable. Therefore, these chips can still be made into a good memory module using 16 chips instead of the regular 8 chips.




In order to make the classification simple, a x8 downgrade DRAM is bit represented by A,B,C, and D. "A" represents DQ0 and DQ1 (data line #0 and data line #1). "B" represents DQ2 and DQ3. "C" represents DQ4 and DQ5. "D" represents DQ6 and DQ7. If a x8 DRAM has DQ0-DQ3 as good bits, the chip would be classified as an "AB". Likewise, a DRAM chip with DQ4-DQ7 good would be classified as a "CD". There are total of 11 combinations:

Four bits good: AB, AC, AD, BC, BD, CD
Six bits good: ABC, ABD, ACD
All eight bits good: ABCD
All eight bits bad: (Blank)

Equipments Used For Downgrade Testing

Downgrade memory chip sorting is usually done in the 3rd world countries where labor rate is low. This is due to the tedious categorization that requires human intervention. The process is also done with very low cost equipments.

First, there is a chip carrier that looks like a memory DIMM module. Instead of soldered down TSOP package DRAM chips, the carrier have TSOP test sockets in their place. Eight chips can be plugged into the 8 sockets. The entire "chip carrier" module is then tested as it were a DIMM module. The test can be performed in two different ways: on a motherboard or on a low cost memory module tester.

The "downgrade" test motherboard is no different from a regular CPU board in hardware. However, the software is quite different. This custom software usually resides in the system "bios" to give direct control on the memory port and thus can directly distinguish the combination of bit failures. The advantage is able to test two carrier modules with 8 chips each at the same time. (Note: a regular DIMM is always needed on the first memory slot to keep the system in operation). Disadvantage is that the test take over ten minutes of test time. Besides, the bios software is normally sold at a high price and obsoletes with each generation of motherboard.

The other way to test is by using a low cost DIMM tester. These testers are normally made to test regular DIMMs. With minimal modification on the test software, the tester can display the good bits in A, B, C, D. The advantages of these testers are fast testing (only a few seconds) and the easy user interface. They are also low cost and compatible to multi-generation and configuration of chips.

Classify By Bad Address

When the most significant address line fails on a DRAM chip, it translates into no access on half of the memory cells. However, the other half of the cells can still be used functionally. Depending on the address stuck high or stuck low, either the upper half or the lower half of the memory cells can be used normally. Therefore, these single address failed chips are classified in two categories:

High - the upper half of the DRAM cells are good.
Low- the lower half of the DRAM cells are good.




Using Downgrade DRAM In Memory Module

The "ABCD" classification chips are usually good enough to be assembled as regular DIMM modules. Although they have failed the original manufacturer test at one time, they are just slightly out-of-spec and usually used in a lightly loaded system (below maximum memory populated condition). These modules are usually marked and sold as "OEM" grade DIMM.




The 4 bits good (example: AB) and the 6 bits good (example: ABC) are used with specially designed DIMM PCB (printed circuit board). In the case of the 4 bits good, it emulated an 8 bits good chip by putting two 4 bits good chips back-to-back to each other. Overall, there are total of 9 different types of special design DIMM PCB to accommodate all nine combinations of partially good chips.

For the "High" and "Low" categories, the DIMM module would be more complicate. A special ASIC chip has to be used to combine the column address lines on two chips and to reconstruct the complete set of good address lines. These ASIC chips are available from small vendors in Taiwan. Two types of PC boards are designed to use this kind of chips. One design covers the "High" address chips and the other one covers the "Low" address chips.

What Happen To The "Not Functional" Chips?

The many DRAM that do not pass the "downgrade" test for memory modules are not completely wasted. These chips are usually sold as "Sweeps", from the phase "sweeping the floor". They might still have some good bits that can be used in audio applications.

Compact Disc (CD) player is an application that only uses 12 bits stream out of a 16 bit chip. They use 4 bits for ECC (error correction code) to keep the data stream on correcting itself. The requirement is to have 4 completely good bits for the ECC.

Digital answering machine is purely digital audio application. User can usually stand a few pops without noticing. Their sorting specification is, therefore, no more than one consecutive bad bit within every 16 bits. One small block of completely good cells is also needed in the first quadrant to host the operating system.

Since DRAM cells usually fail in cluster confined to a small area, consecutive bad cells can be redistributed through address scrambling. This method calls for reconnecting address lines in different sequence to disburse the bad cells into non-consecutive locations.

All the above few applications require custom sorting on DRAM chips. The sorting is done according to specific application needs. High volume usage is usually the criteria to justify this kind of custom sorting with specially designed testing software.

By: Cecil Ho, CST, Inc.
Copyright 2003 CST, Inc. All Rights Reserved

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