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Understanding DDR3 Serial Presence Detect (SPD) Table

Tuesday, July 17, 2007


Since I wrote “Understanding DDR Serial Presence Detect (SPD) Table” in 2003, I have been getting a lot a feedback from readers. I added “Understanding DDR2 Serial Presence Detect (SPD) Table” in 2006.  Some of you told me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses.

Lately, CST has started shipment of a DDR3 EZ Programmer. Since the DD3 DIMM is introduced recently, I think this is the time to add an article for the DDR3 SPD Table. Due to the many more years of development, the DD3 SPD table has definitely got more sophisticated than the original DDR and DDR2 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to accommodate you all.

Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with “Turbo-Tax” type of multiple choices questions. I hope you’ll find it interesting and useful.

Sample Jedec Standard SPD Data Table

Byte 0
Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage

Bit 3 to Bit 0 describes the total size of the serial memory actually used in the EEprom for the Serial Presence Detect data. Bit 6 to Bit 4 describes the number of bytes available in the EEprom device, usually 128byte or 256 byte. On top of that, Bit 7 indicates whether the unique module identifier covered by the CRC encoded on bytes 126 and 127 is based on (0-116byte) or based on (0-125byte)..

(When CST EZ-SPD Programmer is used: Simply select items from 3 tables and automatically calculate the final hex number)

The most common one used is:
Total SPD Bye = 256
CRC Coverage = 0-116Byte
SPD Byte used = 176 Byte
Resulting code is   92h

Byte 1
SPD Revision

Version   0.0              00h
Revision 0.5 
Revision 1.0             
Revision 1.1             
Revision 1.2              12h 

Byte 2
DRAM Device Type
This refers to the DRAM type. In this case, we are only dealing with DDR3 SDRAM.

DDR3  SDRAM:     0Bh    

Byte 3
Module Type

This relates to the physical size, and category of memory module.

Undefined                                00h
RDIMM (Registered Long DIMM)    01h
UDIMM (Unbuffered Long DIMM)  02h
SODIMM (Small Outline DIMM)      03h

Byte 4
SDRAM Density and Banks

This byte defines the total density of the DDR3 SDRAM, in bits, and the number of internal banks into which the memory array is divided.
Presently all DDR3 have 8 internal banks.

SDRAM Chip Size  
512Mb           01h
1Gb               02h  
2Gb               03h
4Gb               04h             

Byte 5
SDRAM Addressing

This byte describes the row addressing and column addressing in the SDRAM Device.

512Mb chips   
13 Row X 10 Column         09h             
13 Row X 12 Column         0Bh
12 Row X 10 Column         01h

1Gb chips        
14 Row X 10 Column         11h
14 Row X 12 Column          13h
13 Row X 10 Column          09h

2Gb chips        
15Row X  10 Column         19h
15 Row X 12 Column         1Bh
14 Row X 10 Column         11h

Byte 6
Reserved       00h

Byte 7
Module Organization

This byte describes the organization of the SDRAM module; the number of Ranks and the Device Width of each DRAM
(When CST EZ-SPD Programmer is used: Simply select number of Ranks and Device Width. It automatically calculate final hex number)

1 Rank module using X8 chips       01h
2 Rank module using X8 chips       09h
1 Rank module using X4 chips       00h  
2 Rank module using X4 chips       08h
4 Rank module using X8 chips       19h
4 Rank module using X4chips        18h
1 Rank module using X16 chips      02h
2 Rank module using X16 chips      10h

Byte 8
Module Memory Bus Width

This refers to the primary bus width of the module plus the additional with provided by ECC
16bit                            01h
32bit                            04h
64bit (no parity)             03h
64bit + ECC (72bit)         0Bh 

Byte 9
Fine timebase (FTB) Dividend / Divisor

This byte defines a value in picoseconds that represents the fundamental timebase for fine grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The granularity in picoseconds is derived from Dividend being divided by the Divisor.

2.5ps       52h
5ps          55h                         

Byte 10
Medium Timebase (MTB) Dividend

Byte 11
Medium Timebase (MTB) Divisor

These byte defines a value in nanoseconds that represents the fundamental timebase for medium grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The two byte forms the Dividend and the Divisor to determine the granularity of the medium timebase.

0.125ns              Byte 10       01h      Byte  11      08h
0.0625ns             Byte 10       01h      Byte  11      0Fh  

Byte 12
Minimum SDRAM Cycle Time (tCK min)

This byte describes the minimum cycle time for the module in medium timebase (MTB) units.
For MTB granularity = 0.125ns (Byte 10 and Byte 11)

DDR3 400Mhz clock (800data rate)                  14h
DDR3 533Mhz clock (1066data rate)                0Fh
DDR3 667Mhz clock (1333data rate)                0Ch
DDR3 800Mhz clock (1600data rate)                0Ah 

Byte 13  
Reserved            00h

Byte 14
CAS Latencies Supported, Low Byte

(When CST EZ-SPD Programmer is used: Simply select all latencies supported from table. Automatically calculate the hi and low byte hex value base on binary number)

Latency 5.6 supported                06h
Latency 6    supported                04h
Latency 6,7 supported                0Ch
Latency 5, 6, 7, 8 supported        1Eh

Byte 15
CAS Latencies Supported, High Byte  00h

Byte 16
Minimum CAS Latency Time (tAAmin)

Minimum CAS Latency based on medium timebase (MTB) units. tAAmin can be read off SDRAM data sheet.
Based on medium timebase of 0.125ns

12.5ns         DDR3-800D        64h          
15ns           DDR3-800E        78h
11.25ns       DDR3-1066E      5Ah
13.125ns     DDR3-1066F       69h
15ns           DDR3-1066G      78h
10.5ns         DDR3-1333F       54h
12ns           DDR3-1333G       60h
13.5ns          DDR3-1333H       6Ch
15ns             DDR3-1333J        78h
10ns             DDR3-1600G       50h
11.25ns       DDR3-1600H       5Ah
12.5 ns        DDR3-1600J        64h
13.75ns       DDR3-1600K       6Eh


Byte 17
Minimum Write Recovery Time (tWRmin)

This byte defines the minimum SDRAM write recovery time in medium timebase (MTB) units. This value is read from the DDR3 SDRAM data sheet.
Based on medium timebase of 0.125ns

tWR min