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DDR2 DIMM SPD Definition

Friday, August 25, 2006

Since I wrote “Understanding DDR Serial Presence Detect (SPD) Table” in 2003, I have been getting a lot a feedback from readers. Some of you told me that you are using this article to train your employees,
and to introduce the mysteries SPD concept to your customers. I feel honored by your responses.
Lately, some of you had encouraged me to add the DDR2 SPD Table. Since the DDR2 DIMM has taken mainstream recently, I think this is the time to add an article for the DDR2 SPD Table. Due to the many more years of development, the DDR2 SPD table has definitely got more sophisticated than the original DDR SPD table. Your attention is required to understand and follow through. I will try to use as much layman language, as I can to accommodate you all.

Picture of a 8pin-SPD EEPROM made by Atmel

Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry.
Most people only know it as the little Eprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the
system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with “Turbo-Tax” type of multiple choices questions. I hope you’ll find it interesting and useful. 

Byte 0
Number of Serial PD Bytes written during module production
This field describes the total number of bytes used by the module manufacturer for the SPD data and any (optional)
specific supplier information. The byte count includes the fields for all required and optional data.
For most manufacturers, they do not insert optional data and the resulting data (in hex) would normally be:
128Byte:    80h      256Byte:    FFh 
Byte 1
Total number of Bytes in Serial PD device
This field describes the total size of the serial memory used to hold the Serial Presence Detect data,
device used is usually 128 Bytes or 256 Bytes with 256 Bytes as the most common.
256 Byte (24C02)
         (34C02)  with Software Write Protect function
         (34C02B)with Reversible Software Write Protect function    :   08h
128 Byte (24C01):       07h    
Byte 2
Fundamental Memory Type
This refers to the DRAM type. In this case, we are only dealing with DDR2 SDRAM.
DDR2  SDRAM:     08h    
Byte 3
Number of Row Addresses on this assembly
This relates to the DRAM size as well as the Refresh scheme of the DRAM.
The best way to discover this is to use the AutoID function of the CST DIMM tester.
You would first run the AutoID on the tester.

You then use the [Edit] [AdrDat] function to display the Row and Column Address counts.
15:  0Fh    14:  0Eh   13:  0Dh 12:  0Ch 
Byte 4
Number of Column Addresses on this assembly
This relates to the DRAM size as well as the Refresh scheme of the DRAM.
The best way to discover this is to use the AutoID function of the CST DIMM tester.
You would first run the AutoID on the tester. You then use the [Edit] [AdrDat] function
to display the Row and Column Address counts. 13:  0Dh   12:  0Ch   11:  0Bh  10:  0Ah   09:  09h
Byte 5
Module Attributes - Number of Physical Banks on DIMM, Package and Height

This is a multi-purpose field that involves calculations and bit combination.
A Flash program combine them together and give you an automatic result after
you have selected the different attributes.

Byte 6
Module Data Width of this assembly
This refers to the number of data bit width on the module. For a standard 8 byte DIMM, 64 bits
would be most common while an 8 byte ECC module would have 72 bits. Some special module might
even have up to 144 bits. In any case, a CST tester Auto ID function would tell you this number
in plain English.
32 bit:    20h     64 bit:   40h    72 bit:    48h    144 bit:    90h
Byte 7
Not available: 00h      
Byte 8
Voltage Interface Level of this assembly
This refers to the power supply voltage Vdd of the DIMM. Standard DDR2 SDRAM module would be SSTL 1.8V
1.8V DDR2:   05h       Recommended Default
Byte 9
SDRAM Device Cycle time
This commonly referred to the clock frequency of the DIMM. Running at its specified CL latency.
5.0 ns (400Mhz): 50h        3.75 ns (533Mhz): 3Dh       3.0 ns    (667Mhz):      30h
2.5 ns (800Mhz): 25h
Byte 10
SDRAM Device Access from Clock (tAC)
This byte defines the maximum clock to data out time for the SDRAM module. You can normally
read off the tAC specification on the Timing Parameter table.
+/-0.6 ns:            60h
+/-0.5 ns:            50h
+/-0.45 ns:          45h
+/-0.40 ns:          40h
Byte 11
DIMM Configuration Type
This is to identify the DIMM as ECC, Parity, or Non-parity. Normally non-parity is related to
64 bit module, Parity and ECC are related to 72 bit or higher memory bit width on the module.
NonECC:     00h                       
ECC:           02h
Address/Command Parity with ECC:      06h
Byte 12
Refresh Rate
This byte describes the module's refresh rate and if it is self-refreshing or non-self refreshing.
Today, most standard modules would be capable of self-refreshing. The refresh time is easily read
from the DRAM manufacturer data sheet. Refresh time can be listed in two different ways.
1. In Refresh Interval Time. For example: 15.6usec. or 7.8usec.
2. In milli-seconds per x Refresh Cycles. For example: 62.4ms in 8K refresh
This can be converted back into refresh interval time with the equation:
Refresh Interval = Total Refresh Period/number of refresh cycles.
15.6 us Self-refresh (4K):     80h    7.8 us Self-refresh (8K):         82h
15.6 us non Self-refresh :     00h    7.8 us non Self-refresh :         02h
Byte 13
Primary SDRAM Width
This refers to the bit width of the primary data SDRAM.
For a standard DIMM module. 4 bits: 04h   8 bits: 08h    16 bits: 10h
Byte 14
Error Checking SDRAM Width
This refers to the bit width of the error checking DRAM. For a standard module,
it is either no ECC bit, or 8 bits on a regular 8 byte module. It can also be 16 bits on
a 144 bit (16 byte) module.
No-ECC:    00h      8bits:    08h    16bits:    10h
Byte 15
Not available:  00h
Byte 16
Burst Lengths Supported
This is indicates the burst length supported. In DDR2, standard DRAM are all 4, 8 burst supported.
4, 8 Burst length supported:     0Ch          
Byte 17
Number of Banks on SDRAM Device
This is referring to the internal bank on the DRAM chip. All modern DDR2 chips under 1Gbit have
4 internal banks. For chips at 1Gbit or above, they have 8 internal banks.
4 Internal Banks:   04h         8 Internal Banks (for 1Gb or 2Gb chips only):   08h
Byte 18
CAS Latency (CL)
This refers to the all the different Cas Latency supported by your chip. This can vary with the
frequency you operate your DIMM. This number can be read off your DRAM data sheet.
CL=3 and 4 supported:                    18h
CL=4 and 5 supported:                    30h
CL=5 and 6 supported:                    60h
CL=5    supported:                          20h
CL=6    supported:                          40h
Byte 19
DIMM Mechanical Characteristics
This defines the module thickness where the maximum thickness includes all assembly parts: devices,
heat spreaders, or other mechanical components. This information together with the DIMM type, allows
the system to adjust for thermal operation specifications.

Byte 20
DIMM type information

This byte identifies the DDR2 SDRAM memory module type.
Each module type specified in this Byte 20 defines a unique index for module thickness specified in Byte 19,
which may be used in conjunction with thermal specifications in Bytes 21 and 47-61 to adjust system operation
conditions based on installed modules.

 Undefined                                                 00h
 Regular Registered DIMM:                         01h
 Regular Unbuffered DIMM:                         02h
 SO-DIMM:                                               04h
 Micro-DIMM:                                            08h
 Mini-Registered DIMM:                             10h
 Mini-Unbuffered DIMM:                              20h
Byte 21
SDRAM Module Attributes
This byte involves 4 main items. Bit 0-1 signifies the number of registers on the DIMM. Bit 2-3 signifies
the number of PLL’s on the DIMM. Bit 4 indicates if any on board FET switch is enabled. Bit 6 indicates
if an analysis probe is installed. In most cases, Bit 4 and Bit 6 are not used. 
The resulting hex code is calculated as follows:
0 PLL chip and  1 Register chip            00h
0 PLL chip and  2 Register chip            01h
1 PLL chip and  1 Register chip            04h
1 PLL chip and  2 Register chip            05h
2 PLL chip and  1 Register chip            08h
2 PLL chip and  2 Register chip            09h
Byte 22
SDRAM Device Attributes –General
This byte is a multi-purpose byte. It includes PASR (Partial Array Self Refresh) , 50 ohm ODT enable and
also support of Weak Driver. The resultant hex code is calculated based on the selection you made.
Supports PASR                   Supports 50 ohm            Supports weak driver         HEX

No                                            No                                         No                          00h
No                                            No                                         Yes                        01h
No                                            Yes                                       No  &nb