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Sunday, December 17, 2017
Memory Industry News
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Multi-layer 3D-NAND takes impractical wafer process time


Wednesday, October 11, 2017

At the Flash Memory Summit this year, Samsung announced its development of 1Tb 3D NAND, which would be used for commercial products launching next year. However, I wonder when the 4Tb 3D NAND will hit the market.

Based on the information available on TLC 512Gb 3D NAND with 64-layer on about 130mm2 die size (from Samsung and Toshiba) and assuming string stacking of 64-layer, I figured that in order to implement the 4Tb NAND chip:

Eight string stacks of 64-layer are needed. Which will make (512Gb x 8) = 4Gb

The total layer then becomes 512-layer on 130mm2 die size

It will take about a year to process a wafer, 5 weeks for memory logic plus 8 times (i.e. 8 string stack of 64-layer) 5 to 6 weeks for a 64-layer cell layer implementation. Therefore, the wafer processing time for a 512-layer will be about 45 to 53 weeks.

If this simple assessment is right, then it is practically impossible to implement the 4Tb NAND chip. If QLC is considered instead of TLC, there will be an improvement of 25 percent at best. So, a 410-layer will be needed for QLC 4Tb 3D NAND and about nine months of wafer processing time.

How about 16Tb 3D NAND? It needs 2,048-layers with four years of wafer processing time.

For the last several decades, NAND has achieved dazzling bit growth under Moore’s Law. When Moore’s Law ends and planar NAND switches to 3D NAND, many people expect 3D NAND will continuously expand its memory scaling in a vertical direction. However, 3D NAND just achieves price parity with planar NAND at 64-layer. Thus, 3D NAND will just start competing on price with planar NAND. And now I am thinking it will be practically impossible to expect 4Tb NAND.

The limitations of 3D NAND scaling seem obvious. Then, will 3D NAND reach the end of its life span? It might not be that far off.

By: DocMemory
Copyright © 2017 CST, Inc. All Rights Reserved

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