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Sunday, March 18, 2018
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New discovery on aging can delay deployment of small geometries

Friday, July 14, 2017

Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below.

Concepts like ‘infant mortality’ and ‘bathtub curves’ are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which basically follows the curves of a bathtub, there is a wide, safe operating time. As the device ages, the failure rate goes up again on the other side.

“The burn-in technique — heating and cycling the semiconductor — accelerated or precipitated those failures,” said Mick Tegethoff, director of AMS product marketing at Mentor, a Siemens Business. “Initially that was key. Then technology got better and better. The processes got better and it became less of an issue.”

While transistor aging and reliability analysis has always been practiced in safety, automotive, and aerospace applications, this was not the case in consumer devices until very recently. But at 10nm and below, it has become a general problem, regardless of the application area.

Specifically, there are three causes of aging in semiconductor devices:

• Negative bias temperature instability (NBTI). This is caused by constant electric fields degrading the dielectric, which in turn causes the threshold voltage of the transistor to degrade. That leads to lower switching speeds. This effect depends on the activity level of the circuits, with heavier impact on parts of the design that don’t switch as often, such as gated clocks, control logic, and reset, programming and test circuitry.

• Hot carrier injection (HCI). This is caused by fast-moving electrons inserting themselves into the gate and degrading performance. It primarily occurs on higher-voltage modes and fast switching signals.

• Time-dependent dioxide breakdown (TDDB). This occurs when high electric fields eventually cause total breakdown of the gate causing catastrophic failure of the transistor.

“At modern geometries, the primary root cause of all these effects is the stress effect of high electric fields across the dielectric,” said João Geada, chief technologist at Ansys. “As geometries have got smaller, but voltages have not scaled at the same rate, the electric field across gates has increased, resulting in worse aging behavior.”

On top of that, new applications of advanced semiconductors in industrial IoT and automotive spaces, which have formal requirements for durability of parts, has put a critical focus on aging behavior and the ability to predict and/or control it. “It is one thing if a disposable gadget stops operating after a couple of years,” he said. “It is an entirely different issue if a life-critical ADAS system fails, either completely or by failing to meet its minimum operating requirements, within its expected lifetime.”

As with all changes in technology, there is a learning curve. Even established finFET nodes are revisiting reliability.

“We’ve seen a lot of renewed interest in reliability, even from the 16nm node, because you’ve gone from having planar devices that everyone’s been designing with now for many many years — and they’re experienced with — to devices that are three-dimensional,” said Art Schaldenbrand, senior product marketing manager for the Custom IC and PCB Group at Cadence. “Change is a little bit scary. There are also impacts that come with everything scaling down. We have to obey the laws of physics, and sometimes it’s difficult because we don’t understand what the rules are.”

Device stresses are different than in the past, and they are being used in new ways. “If you’re in an application like a chip for industrial IoT, you might sit quietly for 10 years working very little of the duty cycle, but it is aging during those 10 years even when mostly at rest,” he said. “So it’s not just the technology. There are also more challenging applications.”

By: DocMemory
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