Memory FAQs
 
Home
News
Products
Shop
Memory
Corporate
Contact
 

News
Industry News
Publications
CST News
Help/Support
Member Area
Tester Brochure
Demo Library
Software
Tester FAQs

biology medicine news product technology definition

Sunday, October 22, 2017
Memory Articles and Publications
Email ArticlePrinter Format PreviousNext

Recognizing DDR Memory Modules Part-3


Wednesday, May 23, 2001

Part-3

Identifying DIMM Module by Label

JEDEC has also issued a standard for labeling the DDR DIMM module. A standard DDR DIMM module should have at least one label on the module. The label should contain the following information:



Where:
“wwww” = Module Bandwidth
1600: 1.6GB/sec or 2100: 2.1GB/sec.

“m” = Module Type
R= Registered DIMM
U= Unbuffered DIMM (no register on DIMM)

“aa” = SDRAM CAS Latency, with no decimal point (25=2.5ns CAS Latency)

“b” = SDRAM minimum tRCD specification (in clocks)

“c” = SDRAM minimum tRP specification (in clocks)

“d” = JEDEC SPD Revision used on this DIMM

“e” = Gerber file used for this design (if applicable)
A= Reference design of R/C ‘A’ is used for this assembly
B= Reference design of R/C ‘B’ is used for this assembly
C= Reference design of R/C ‘C’ is used for this assembly
D= Reference design of R/C ‘D’ is used for this assembly
E= Reference design of R/C ‘E’ is used for this assembly
F= Reference design of R/C ‘F’ is used for this assembly
H= Reference design of R/C ‘H’ is used for this assembly
K= Reference design of R/C ‘K’ is used for this assembly
Z= Reference design of R/C ‘Z’ is used for this assembly

“f” = Revision number of the reference design used:
1 = 1st revision ( 1st release)
2 = 2nd revision (2nd release)
3 = 3rd revision (3rd release)
Bank= Not Applicable (used with ‘Z’ above)

Example: PC1600R-25330-A1
Is a PC1600 DDR Registered DIMM with CL=2.5, tRCD=3, tRP=3
Using the latest JEDEC SPD Revision 0.0 and produced based on the “A” raw card Gerber, 1st release.


A Note on Module Bandwidth
In theory, higher memory bandwidth will deliver better performance for the computer system. Memory peak bandwidth is defined as memory bus width/8 bits x data rate.

That translates into how fast your 3D games will react, how smooth your MP3 music will play or how good a motion picture you can play in your MPEG video streaming. Bandwidth calculation: memory bus width/8 bits x data rate.

For example: memory bus width for the 184pin DDR module is 64bits, data rate of the DDR SDRAM is usually 266MHz. That makes the peak bandwidth = 64/8X266MHz = 2100MHz.


Click here to find out more about Part-4



By: DocMemory
Copyright © 2001 CST, Inc. All Rights Reserved

Email ArticlePrinter Format PreviousNext
Latest Publication News
Next big thing for DDR4 Memory – 3DS DDR4 Devices11/20/2015
Challenges of testing mobile memories1/15/2014
Understanding DDR4 Serial Presence Detect (SPD) Table11/25/2013
What is Hybrid DIMM Memory Module ?3/19/2013
What is DDR4 Memory ?3/18/2013
New Memory Module Picture 20131/21/2013
Challenges of testing mobile memories2/8/2012
What is LPDDR Memory ?7/20/2011
Determine Endurance on a NAND Flash Chip4/5/2010
Smartphone Memory and Test Challenges4/5/2010

CST Inc. Memory Tester DDR Tester
Copyright © 1994 - 2017 CST, Inc. All Rights Reserved